1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop circuit (hereinafter referred to as ‘DLL’) of a semiconductor memory device.
2. Description of the Related Art
Generally, in a double data rate synchronous DRAM (DDR SDRAM, hereinafter referred to as a synchronous semiconductor memory device), data read and write operations are performed by an internal clock signal that is synchronized with an external clock signal. More specifically, a read and write operation is performed every half cycle of an internal clock signal. A DLL having a delay characteristic is used for generating this internal clock signal. In order to accurately synchronize output data of a synchronous semiconductor memory device with an external clock signal, the DLL comprises a delay element requiring delay compensation in its feedback loop. For example, the delay element may comprise an output driver.
The conventional DLL comprises a variable delay circuit, a phase detector, a control circuit, and a replica output driver.
The replica output driver included in the feedback loop in the DLL replicates, or copies, the delay of an internal clock signal which is delayed through the output driver of the synchronous semiconductor memory device.
The phase detector detects the phase difference between the internal clock signal delayed through the replica output driver, and the external clock signal. The control circuit generates a control signal for controlling the delay amount of the variable delay circuit in response to the output signal of the phase detector. In response to the control signal, the variable delay circuit delays the external clock signal and generates an internal clock signal that is synchronized with the external clock signal.
Meanwhile, in response to a driver impedance control signal generated by a mode register included in the semiconductor memory device, the output driver of the synchronous semiconductor memory device can change its driving strength. As the driving strength of the output driver changes, the impedance of the output driver changes and it may cause a delay in the internal clock signal of the output driver. However, since the replica output driver included in the conventional DLL is not separately controlled by the driver impedance control signal, it cannot copy the delay of the internal clock signal with respect to the variation of impedance of the output driver. That is, the replica output driver may not accurately track the output driver. Accordingly, for this reason, the output data of the synchronous semiconductor memory device cannot be accurately synchronized with the external clock signal.